----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:04:10 10/12/2018 
-- Design Name: 
-- Module Name:    feu_final - Bhv 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity blinker is
	port(Clk100MHz, PB_0 : in bit;
	LED_0 : out bit);
end blinker;

architecture Behavioral of blinker is
	alias reset is PB_0; -- alias pour le signal de rinitialisation
	signal clk_out : bit := '0'; -- signal d'horloge aprs division

	-- Constante de division, ici pour une sortie  1Hz.
	constant clock_divisor : integer := 100000000;
begin
	-- Diviseur de frquence : divise la frquence du signal Clk100MHz par clock_div.
	clock_divider : process(Clk100MHz, reset)
	variable c : integer range 0 to clock_divisor - 1 := 0;
	begin
	if reset = '1' then
		c := 0;
		clk_out <= '0';
	elsif (Clk100MHz'event and Clk100MHz = '1') then
		if c < (clock_divisor - 1) / 2 then
			c := c + 1;
			clk_out <= '0';
		elsif c = (clock_divisor - 1) then
			c := 0;
			clk_out <= '0';
		else
			c := c + 1;
			clk_out <= '1';
		end if;
	end if;
	end process;
	-- Sortie sur la LED
	LED_0 <= clk_out;

end Behavioral;


entity feux is
port(clk, PB_0, PB_2, PB_3 : in bit;
	LED_3210, LED_7654 : out integer range 0 to 7);
end feux;

architecture rouge of feux is

begin
process(clk, PB_0)
-- variables
variable compteur : integer range 0 to 20;
variable etat : integer range 0 to 3;
begin
	if(PB_0 = '1') then
		case etat is
			when 0 => compteur := 0; etat := 0;
			when 1 => compteur := 0; etat := 0;
			when 2 => compteur := 18; etat := 3;
			when 3 => -- On ne fait rien
			when others => compteur := 0; etat := 0;
		end case;
--		compteur := 0;  etat := 0;
	elsif(clk'event and clk='1') then
		case etat is
			when 0 => if (compteur > 7 and PB_3 = '1') then
					etat := 1;
					compteur := 7;
				end if;
			when 1 => if (compteur > 9) then
					etat := 2;
				end if;
			when 2 => if (compteur > 17 and PB_2 = '1') then
					etat := 3;
					compteur := 17;
				end if;
			when 3 => if (compteur > 19) then
					etat := 0;
					compteur := 0;
				end if;
			when others => etat := 0; compteur := 0;
		end case;
		compteur := compteur + 1;
		end if;	
		
		case etat is 
			when 0 => LED_3210 <= 1; LED_7654 <= 4;
			when 1 => LED_3210 <= 2; LED_7654 <= 4;
			when 2 => LED_3210 <= 4; LED_7654 <= 1;
			when 3 => LED_3210 <= 4; LED_7654 <= 2;
		end case;
		end process;
end rouge;


entity feu_final is
	port(Clk100MHz, PB_0, PB_2, PB_3 : in bit;
	LED_3210, LED_7654 : out integer range 0 to 7);
end feu_final;

architecture Bhv of feu_final is

	component blinker is
	port(Clk100MHz, PB_0 : in bit;
		LED_0 : out bit);
	end component blinker;
	
	component feux is
	port(clk, PB_0, PB_2, PB_3 : in bit;
		LED_3210, LED_7654 : out integer range 0 to 7);
	end component feux;
	
signal clock : bit;

begin
	C1 : blinker port map(Clk100MHz, PB_0, clock);
	C2 : feux port map(clock, PB_0, PB_2, PB_3, LED_3210, LED_7654);
end Bhv;